1. Field of the Invention
The present invention relates to the technical field of processors and, more particularly, to an energy-efficient nonvolatile microprocessor with a processing core which is provided with a memory map containing a reset entry and a system states recovery entry directed to an expected handling process. When a power source is recovered to a stable state, the processing core starts with the system states recovery entry to execute the expected handling process for overcoming different system states recovery exceptions generated by the microprocessor in different application situations. The energy-efficient nonvolatile microprocessor makes use of a system states partition (SYSPA). When the power source is unstable, the processing core only stores the programmer visible states, so as to effectively save the area of a nonvolatile flip-flop array and the energy consumption required for storage. Another energy-efficient method is provided to store the system states of peripheral modules corresponding to the bits of the store-enable register that are set to be “true” into the nonvolatile flip-flop array.
2. Description of Related Art
With development of low-power IC designs, modern living is full of a variety of novel electronic apparatuses and application scenarios, such as wearable devices, implantable devices, ambient sensors, home automation, wireless body area networks (WBANs), Internet of things (IoT), and the like. Such electronic apparatuses are equipped with difference functions and requirements based on different application scenarios. Therefore, the cost is high and it is inefficient to design application specific integrated circuits (ASICs) for a dedicated application only. With the microprocessors, it is able to satisfy the system requirements in different application scenarios by programing the embedded software in operation and changing the arrangement of modules cooperated with the microprocessors. Accordingly, the microprocessors are used as a system operating core in general.
By analyzing the application scenarios, it can be seen that the application mode is typically a periodic task. In one cycle, the actual active time is much shorter than the idle time for the system. For example, in the wireless body area network (WBAN) applications, the sample rates of the sensors used are typically in the range of several Hz to several KHz. Thus, such applications are also known as low duty-cycle applications.
In the low duty-cycle applications, a microprocessor is mostly at idle state. In general, the system uses a battery or an energy harvesting technique as a power source. Thus, it is an essential design approach for a microprocessor to increase the battery lifetime by reducing the system power consumption and maintain the system operation with limited extracted energy.
Currently, in common low-power microprocessor designs, there are many techniques capable of effectively reducing the dynamic power consumption, such as clock gating, dynamic voltage frequency scaling, and standard cell library for special designs. In general, the total power consumption for a system can be divided into dynamic power consumption and static power consumption. However, in the low duty-cycle applications, the system is mostly at idle or standby state, so that its static power consumption occupies the majority of total system energy. Accordingly, reduction on the static power consumption is more important than that on the dynamic power consumption for the system.
In the static power consumption reduction, one of the efficient and widely used approaches is to power off the system, either in external power-off or in virtual VDD off by a power gating technique, which can effectively reduce the power consumption to achieve the purpose of reducing the static power consumption. However, the power-off behavior may cause a loss of data stored in the internal flip-flops and SRAMs and further a loss of system states. Accordingly, when the microprocessor has to be recovered from the power-off mode to an active state, it is necessary to execute a rebooting process. Based on the complexity of the microprocessor system, the booting process takes the time in a range from hundreds of microseconds to a few seconds. The energy and operating time consumed by the system during the booting process leads to a huge amount of overheads.
Recently, a novel nonvolatile microprocessor is proposed, with which an emerging nonvolatile memory or nonvolatile flip-flop is embedded in the system, so as to rapidly store the system states in the merging nonvolatile memory just before power-off. Next, the system enters in the power-off mode to save the static power consumption. Since the nonvolatile memory can keep the internal data after power-off, the system can quickly read data from the nonvolatile memory and restore its active states as needs, such that the overhead required for the booting process is eliminated. Hence, the problems of static power consumption and booting overhead are overcome.
From the above description, it is known that the nonvolatile microprocessors have three new characteristics in normally-off computing: (1) zero standby power; (2) instant on-off feature; and (3) resilient to power failure.
Current implementation of nonvolatile processors is divided into main memory level implementation, flip-flop/register level implementation, and combination thereof.
The main memory level implementation is provided to arrange the nonvolatile memory in a level as same as the main memory level. The nonvolatile memory has the features of random access, high access speed, and nonvolatile data storage. Therefore, in M. Zwerg, A. Baumann, R. Kuhn, M. Arnold, R. Nerlich, M. Herzog, R. Ledwa, et al. “An 82 uA/MHz Microcontroller with Embedded FeRAM for Energy-Harvesting Applications” issued in Proc. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 334-36, 2011, a ferroelectric random access memory (FeRAM) is used as a data memory and program memory in the system. Thus, when a processing unit of the microprocessor performs store and restore operations, it has to use a bus for access to a nonvolatile memory, and the data access to the nonvolatile memory requires more time and energy to complete the store and restore operations.
The flip-flop/register level implementation is divided into a fully replacement method and a parallel compare and compress Codec (PACC) method.
The fully replacement method is provided to fully store the system states at flip-flop/register level. In W. Yu, S. Rajwade, S.-E. Wang, B. Lian, G-E. Suh, and E. Kan “A non-volatile microcontroller with integrated floating-gate transistors” issued in Proc. International Conference on Dependable Systems and Networks Workshops (DSN-W), pp. 75-80, 2011, an Xilinx PicoBlaze-based configuration is used to implement a nonvolatile microprocessor, which replaces all memory cells in the based configuration with 989 floating-gate nonvolatile flip-flops. The memory cells include general purpose registers (GPRs), a scratch pad, a system stack, a conditional register (Cond), an instruction register (Inst. reg), and a program counter (PC). The floating-gate nonvolatile flip-flops need a higher driving voltage (6V), and thus a power monitor, a nonvolatile (NV) controller, and charge pumps are added.
However, the nonvolatile flip-flops occupy a huge area, so that the fully replace method has a vast area overhead. In Y. Wang, Y. Liu, Y. Liu, D. Zhang, S. Li, B. Sai, M.-F. Chiang, and H. Yang “A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors” issued in Proc. Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1519-1524, 2012, it is observed that the system states inside the system remain the same as the original reset states over an 80% probability when the system is running Hence, after the system states and a preliminary state table are performed with an XOR operation, a large amount of continuous 0s or 1s are obtained due to the same states. In this case, the compare and compress Codec (PACC) method can take a data compression through a run length coding algorithm and implement parallel running length coding (PRLC) Codec with a parallel process, thereby reducing the number of required nonvolatile flip-flops for area reduction consideration.
In implementing a nonvolatile logic array (NVL array) by combining the main memory level and flip-flop/register level implementations, it uses many small memory arrays to store the system states, which can increase the data transmission bandwidth in store and restore operations. In S. C. Bartling, S. Khanna, M. P. Clinton, S. R. Summerfelt, J. A. Rodriguez, and H. P. McAdams “An 8 MHz 75 uA/MHz Zero-leakage Non-volatile Logic-based Cortex-M0 MCU SoC Exhibiting 100% Digital State Retention at VDD=0V with <400 ns Wakeup and Sleep Transitions” issued in Proc. International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 432-433, 2013, it implements the nonvolatile microprocessor based on the Cortex-MO instruction set and adds ten FeRAM-based nonvolatile logic (FeRAM NVL) arrays each having 8×32-bit memory size. The ten FeRAM NVL arrays are in charge of state storage or backup of 2537 flip-flops (FFs). The functions of self-test (BIST) and error correcting code (ECC) are built in the FeRAM NVL arrays to increase the system testability and reliability.
In the nonvolatile microprocessors as cited above, only their hardware designs are considered for most situations, which are focused on replacing conventional volatile devices with nonvolatile devices. For the operation of a nonvolatile microprocessor after the system is restored, the prior art directly restarts from the time point of storing the system states. However, in the real applications, the microprocessor is not a stand-alone unit and often cooperates with a number of peripheral modules such as a tri-axial accelerator, a temperature sensor, and the like through the communication interfaces including UART, SPI, and I2C.
In some system applications, the microprocessor is responsible of time-related works in the real world such as a light control of street lights or billboards. It can be seen that the system states are equivalent to be suspended at the time point of storing them in the nonvolatile storage.
Accordingly, after a period of time, the system takes the states recovery action. The nonvolatile processor itself recognizes the time as the time point of storing the system states, which may encounter a problem that the communication interfaces between the nonvolatile microprocessor and its cooperated modules are not in synchronization or, in the actual time related applications, a time difference exists between the time recognized by the nonvolatile microprocessor and the actual time. Such problems result in an abnormal operation after the system states are restored, which is known as system state recovery exceptions, which may cause the system to be operated abnormally.
In the prior papers, the nonvolatile microprocessors are all implemented to restart directly from the location where the system states are stored. Such implementations cannot make sure the program entry point after the system restore, and thus the programmer is unable to insert a fragment of handling process after the system states are recovered.
FIG. 1 is a schematic diagram illustrating an operation of state recovery of a typical nonvolatile microprocessor. Label (1) indicates that the system runs at an address of 0xA200 before power off, and in this case the system stores the system states first and then powers off. Label (2) indicates that the power source is recovered, and the system restores the stored system states. Label (3) indicates that the system restarts from the address executed before power off, i.e., executing the address immediately following 0xA200. The system may encounter an unexpected power interruption at any time point, and thus its execution point is not fixed before the power is suddenly shunted down, so that the program entry point is not known after the system is restored. Therefore, after the system states are recovered, the programmer is unable to insert a handling process. In addition, the nonvolatile processor itself recognizes the time as the time point of storing the system states, which may encounter a problem that the communication interfaces between the nonvolatile microprocessor and its cooperated modules are not in synchronization, or a time difference exists between the time recognized by the nonvolatile microprocessor and the actual time. Accordingly, when Label (4) is executed, the system will produce an unexpected exception, which causes the system operation to encounter failure, instability or even crash.
Therefore, it is desirable to provide an improved nonvolatile microprocessor to mitigate and/or obviate the aforementioned problems.